1. Field of the Invention.
This invention relates generally to the field of frequency synthesizers, and more specifically to those synthesizers wherein the output is a binary pulse train having a frequency which is a controllable fraction of the frequency of an input pulse train.
2. Background of the Invention.
Rate multipliers, which provide an output pulse train having a frequency which is some fraction of the frequency of an input pulse train, are well known in the prior art. Generally, such rate multipliers provide an output which is 2.sup.n weighted, that is, binary, quaternary, octal, hexadecimal, etc., although some decimal-weighted rate multipliers are also known.
Rate multipliers found in the prior art usually include shift registers whose stages may be required to change state at the clocking rate. Attempts at increasing this clock rate results in the circuit's becoming unreliable above certain clock rates, which rates are determined by the particular semiconductor technology involved. Finally, those rate multipliers found in the prior art which may be cascaded in order to divide the input pulse rate into a greater number of segments uniformally require all succeeding segments to be operated at the same clock rate as the original segment. Because the cost of such elements is normally related to the speed at which they will operate, increasing the multiplication factor by adding additional segments significantly increases the cost of the total device. It is desirable to have a rate multiplier capable of operating at high speeds with large multiplication factors, but which may be produced at a lower cost than those currently known in the prior art.